Kod: Markera allt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; -- 4 bitars SAR
entity sar4 is port(
clk_50, data, startn: in std_logic; -- startar konvertering vid startn = '0'
convc: out std_logic:='0'; -- convc visar '0' efter avslutad konvertering
dout: out std_logic:='0'; -- seriell utgång
clk: out std_logic; -- klockutgång
dig_out: out std_logic_vector(3 downto 0)); -- 4 bitars parallell utgång
end sar4;
architecture state_machine of sar4 is
type StateType is (data0, data1, data2, data3, idle); -- 5 olika tillstånd
signal state :StateType;
signal slow_clk :std_logic_vector(2 downto 0);-- skalar ned klockfrekvensen 8 ggr
begin
state_shift:process(clk_50)
begin
if rising_edge(clk_50) then
if (slow_clk = 0) then
case state is
when idle =>
dout<='1';
if (startn = '0') then
state <= data3;
dig_out<="0111";
convc<='1';
else
state <=idle;
end if;
when data3 => dig_out(3)<=data; dig_out(2)<='0';
state <=data2;
dout<= data;
when data2 => dig_out(2)<=data; dig_out(1)<='0';
state <=data1;
dout<= data;
when data1 => dig_out(1)<=data; dig_out(0)<='0';
state <=data0;
dout<= data;
when data0 => dig_out(0)<=data;
state <=idle;
dout<= data;
convc<='0';
when others =>
state <=idle;
end case;
end if;
slow_clk<=slow_clk+1;
clk<=slow_clk(2);
end if;
end process state_shift;
end state_machine;Hälsn,,
