Xilinx ISE + Verilog = nej.

PIC, AVR, Arduino, Raspberry Pi, Basic Stamp, PLC mm.
bos
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Blev medlem: 24 februari 2007, 23:29:15
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Xilinx ISE + Verilog = nej.

Inlägg av bos »

Förstagångsanvändare på Xilinx ISE här (har använt Quartus Prime innan), och jag är lite förvirrad när jag försöker peta på ett testprojekt att leka med.

Det jag har gjort är att skapa nytt projekt, välja en Xilinx CPLD-krets (XC2C32-...), skapa en ny verilog-source och definierat in-/utgångar, skapat en ucf-fil (Project->New source->ICF) som är helt tom. Därefter högerklickar jag på icf-filen för att mappa pinnarna, och där får jag felet (se nedan).

Om jag gör exakt samma procedur som ovan, fast med VHDL istället, går det bra; jag får upp PACE och kan mappa pinnarna. Men Verilog vägrar, och jag förstår inte ens varför.

Krävs det någon extra inställning för att få ISE att tycka om Verilog?


Kod: Markera allt

Started : "Synthesize - XST".
Running xst...
Command Line: xst -intstyle ise -ifn "T:/FPGA/KeymasterC64/Main.xst" -ofn "T:/FPGA/KeymasterC64/Main.syr"
Reading design: Main.prj

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "Main.v" in library work
Module <Main> compiled
No errors in compilation
Analysis of file <"Main.prj"> succeeded.
 

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <Main>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <Main>.
    Related source file is "Main.v".
Unit <Main> synthesized.


=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <Main> ...

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Process "Synthesize - XST" completed successfully

Started : "Translate".
Running ngdbuild...
Command Line: ngdbuild -intstyle ise -dd _ngo -uc Main_icf.ucf -p xc2c32-VQ44-4 Main.ngc Main.ngd

Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
-intstyle ise -dd _ngo -uc Main_icf.ucf -p xc2c32-VQ44-4 Main.ngc Main.ngd

Reading NGO file "T:/FPGA/KeymasterC64/Main.ngc" ...
Loading design module "T:\FPGA\KeymasterC64/Main.ngc"...
WARNING:NgdBuild:578 - Design contains no instances.
Gathering constraint information from source properties...
Done.

Annotating constraints to design from ucf file "Main_icf.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
Done...

Checking expanded design ...
ERROR:NgdBuild:605 - logical root block 'Main' with type 'Main' is unexpanded.
   Symbol 'Main' is not supported in target 'xbr'.

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     1
  Number of warnings:   1

Total REAL time to NGDBUILD completion:  3 sec
Total CPU time to NGDBUILD completion:   2 sec

One or more errors were found during NGDBUILD.  No NGD file will be written.

Writing NGDBUILD log file "Main.bld"...

Process "Translate" failed
ERROR: required results from Translate are not available, Open Source operation cancelled.